Aims and Scope

Formal Specification and Verification is a well-established field, which has produced considerable impact on current technology and applications. Formal program specification tools relying on semi-automated proof are considered as standards of deployment for safety-critical applications. At the same time, model checking has been successfully used for more than a decade in the verification of hardware and software robustness.

Recently, these techniques have been adopted (and adapted) in other research areas such as multi-agent system verification and symbolic analysis of network processing specifications. In the first area, verification can be tailored to investigate the power of agents in strategic interactions, with potential applications in economics, negotiation and strategic voting, to name only a few. In the latter area, verification is used guarantee the correctness of the functionality of the network.

The workshop is aimed at attracting high-quality research work, both theoretical and applied, which focuses on novel specification and verification techniques, with a particular emphasis on techniques and approaches for the design, implementation, analysis, testing, and maintenance of software systems.

SVM 2015 will be held in conjunction with the 20th International Conference on Control Systems and Computer Science (CSCS 20) in Bucharest, Romania, 27-29 May 2015,